1. Field of the Invention
This invention relates generally to a unique memory output integrated circuit of the type which may be fabricated from complementary metal oxide semiconductor devices and diodes utilizing silicon on sapphire technology and which may be interfaced with an array comprised of a plurality of memory cells.
2. Description of the Prior Art
Conventional integrated circuit, high speed random access memories have been known to include an associated memory output circuit of the type by which data may be read from an array of memory cells through the utilization of differential sensing of large transient signals between both a first data BIT bus line and a relatively opposite state second data BIT bus line. The data bus lines are connected to respective ends of each of the memory cells comprising the memory array. Several disadvantages are known to occur by using the conventional memory cell arrangements and their associated memory output circuits.
Since both of the BIT and BIT bus lines are utilized by the conventional output circuits for differential signal sensing, a relatively symmetrical memory cell has heretofore been required so as to be adapted to rapidly discharge either the BIT or the BIT bus lines during the read operation. Consequently, this has resulted in relatively large memory cell areas and increased costs per integrated circuit. Moreover, the associated conventional memory output circuits have included the use of relatively large numbers of logic gates and transistors so as to be capable of being interfaced with both the BIT and BIT bus lines. Consequently, the additional number of gates and other components have been known to inherently increase the time delay required for which data could be read out of a discrete memory cell.